Decimal Multiplication in FPGA with a Novel Decimal Adder/Subtractor

Financial and commercial data are mostly represented in decimal format. To avoid errors introduced when converting some fractions to binary, these processed with arithmetic. Most processors only have hardwired binary arithmetic units. So, operations executed slow software-based functions. For the fast execution of operations, dedicated hardware units been proposed designed FPGA. Decimal multiplication is found most decimal-based applications so its optimized design very important for execution. In this paper two new parallel multipliers FPGA proposed. These based on a adder/subtractor also paper. The improve state-of-the-art multipliers. Compared previous architectures, implementation results show that achieve 26% better area 12% performance. Also, reduce performance gap smaller 32 digit operands.